Throughput limits on 82586: real or imaginary?

Harry Saal (hjs@lindy.Stanford.EDU)
Tue, 1 Nov 88 21:52:24 PST

Drawing conclusions about the relative capabilities of the Intel 82586
vs. Lance based on two different controller subsystem designs doesn't
truly indicate the limits or lack thereof in these chips.

Whether the 82586 is able to keep up with high traffic rates depends on the
surrounding hardware design (to minimize bus latency and wait states) and
on the driver software; there is nothing inherent in the design of the
chip itself that prevents indefinite reception of back-to-back packets. We
do it in the Sniffer (at least in highspeed mode), but it does require a
fair degree of heroics and a careful reading of the latest bugsheet from
Intel; some modes will generate "dma overrun" regardless of how fast the
memory bus is.

On the transmit side, though, we have not been able to generate
back-to-back packets; the minimum interframe spacing that a single 82586
can manage seems to be about 40 usec instead of 9.6. For us that's no big
deal since we're just trying to generate traffic to load the network, and

This archive was generated by hypermail 2.0b3 on Thu Mar 09 2000 - 14:43:57 GMT