Re: IP protocol on a chip(s)


Erik E. Fair (fair@ucbarpa.Berkeley.EDU)
9 Dec 87 13:10:38 GMT


In the referenced article, david@elroy.Jpl.Nasa.Gov (David Robinson) writes:

>To increase TCP/IP performance has anyone looked into making an IP
>protocol chip or chipset?

Greg Chesson of Silicon Graphics in Mountain View, CA has been
looking into this. He gave a paper at the Summer 1987 USENIX
Conference in Phoenix, entitled "Protocol Engine Design." The paper
starts on page 209 in the proceedings from that conference, which
are available from the USENIX Association. His design goal was to
produce a chipset capable of keeping up with FDDI data rate
(100Mbit/sec) by doing protocol processing in a packet-time.

The technology he described was reported sold by Silicon Graphics
two months ago to a company called "Protocol Engines, Inc." in
Santa Barbara, CA. Greg Chesson's reply to an inquiry I made about
the sale was as follows:

-------------------------------------------------------------------------------

Date: 23 Oct 87 22:47:56 GMT
From: sgi!greg@ucbvax.berkeley.edu (Greg Chesson)
Organization: Silicon Graphics Inc, Mountain View, CA
Subject: Re: Greg Chesson's Protocol Engine technology sold by SGI
Message-Id: <7237@sgi.SGI.COM>
References: <21255@ucbvax.BERKELEY.EDU>

to: Erik Fair, Dave Farber, and others:

The newspaper article quoted in this news group created some undeserved
speculation and masked the enthusiastic and public spirited support
that SGI has for the project and the concept. SGI has given over
protocol engine technology to Protocol Engines Inc for nominal
reimbursement of costs. It was not a significant financial
transaction. SGI engineers and people at other companies continue to
work on the project.

Protocol engine details - protocol, state machines, software emulation
- will be placed in the public domain as has been stated before. PEI
is modeled after other multi-company consortia such as the group that
standardized the SCSI bus. It is a corporate shell intended to achieve
the following:
        1) provide a neutral repository for P-engine technology

        2) fund chip fabrication

        3) focus on standards activities

        4) provide multiple sources for chips

        5) push the technology beyond 100 Mbit/sec

Item (1) helps preserve the open nature of the design and to ensure
that there exists an organization dedicated to P-engine technology.
Item (2) should be obvious, since prototype production is more than I
can accomplish as an internal skunkworks. Item (4) means that PEI is
working with semiconductor houses to make P-engines become standard
products. The other items should be self-explanatory.

        Greg Chesson Silicon Graphics 2011 Stierlin Road Mountain View,
        Ca, 94043 (415)962-3496 {sun,pyramid,adobe,allegra,decwrl}!sgi!greg

-------------------------------------------------------------------------------

If you (or anyone else) knows about other efforts in this general
direction, I would appreciate hearing about it.

        Erik E. Fair ucbvax!fair fair@ucbarpa.berkeley.edu



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